Frequently Asked Interview Questions: Electronics and VLSI
Here I am giving you some questions which are asked most frequently in almost all interviews in the core companies. All these questions are very basic questions and there are a lot of derivative questions which generates from these basic questions.
Q.1 What is AND gate? Is it a multiplier or adder?
Q.2 What are digital logic levels? How logic level ‘1’ and logic level ‘0’ is decided in a digital circuit?
Q.3 Design a NAND gate using CMOS circuit?
Q.4 Design a NOR gate using CMOS circuit?
Q.5 What is V-I characteristic is a n-mos transistor?
Q.6 Define cut-off, active and saturation region of a n-MOS transistor?
Q.7 In which domain of MOS characteristic any digital circuit works?
Q.8 In which domain of the MOS characteristic any Analog circuit works?
Q.9 What is threshold voltage of any MOS transistor?
Q.10 What is a latch?
Q.11 What is a flip flop?
Q.12 Why flip flop is a edge triggered device?
Q.13 Make a timing diagram of a latch device?
Q.14 Make a timing diagram of a flip flop device?
Q.15 What is the setup time?
Q.16 What is the hold time?
Q.17 On which parameter setup time depends?
Q.18 On which parameter hold time depends?
Q.19 How to fix a setup violation in a digital circuit?
Q.20 How to fix a hold violation in a digital circuit?
Q.21 How to fix the setup violation on silicon?
Q.22 How to fix the hold violation on silicon?
Q.23 What is a MUX?
Q.24 Design a MUX using AND gate?
Please visit http://www.incise.in/ for knowing the answers. Or write me at rakesh.adhikari@incise.in
http://www.incise.in/contactus.html
Please visit http://www.incise.in/ for knowing the answers. Or write me at rakesh.adhikari@incise.in
http://www.incise.in/contactus.html
INCISE INFOTECH PVT. LTD. |
A-38 , 1st Floor, Sector-4, Noida |
E-mail: register@incise.in |
Answer1> An AND gate is neither a multiplier nor an adder.It is simply a circuit which performs the "." operation for two or more binary logic levels.
ReplyDeleteFor example:An AND gate can never multiply 5 and 4 nor can it add 5 and 4.Yes we can say that these voltages can be used to decide the logic levels for that particular gate depending upon the threshold voltage...
Answer2> Digital logic levels are nothing but are notations to represent voltage levels,these logic levels are basically used to define the the cut-off and the saturation region of the MOS.
ReplyDeleteLogic'0' is the voltage level in which the p-mos is in the saturation region and the n-mos is in the cut-off region,and logic'1' is the voltage level in which the n-mos is in the cut-off region and the p-mos is in the saturation region....
Logic levels are basically decided on the basis of the threshold voltage of a particular MOS.For example:In case of a n-mos the logic'0' is the voltage below the threshold voltage but logic'1' is not the voltages above the threshold voltage,logic'1' of the mos depends upon the characteristic graph of that n-mos.
Latches and Flip-flops:
ReplyDeleteLatches have level sensitive control signal input means latch is a level triggered device.
Flip-flops have edge sensitive control signal input means flip flop is an edge triggered device.
Flip-flops and latches which use this control signals are called synchronous circuits. So if they don't use clock inputs, then they are called asynchronous circuits.
This comment has been removed by the author.
ReplyDeleteThis comment has been removed by the author.
ReplyDeleteThe set up and hold time is the characteristic of flip flops.Set up and hold time are defined for flip flops.These are the requirement of flip flops to function properly.
ReplyDeleteSET UP TIME:The minimum required time, the input data should be stable(or held valid) before the clock edges is called set up time.
HOLD TIME:The minimum required time the input data should be stable(or held valid) after the clock edges is called hold time.
Set up violation in digital circuits can be fixed by:
ReplyDelete1)by delaying the clock.
2)by reducing the clock frequency.
Multiplexer is a logic ckt that recieves binary information from several inputs and transmits information to a single output.The input seleted is controlled by a set of selected inputs therefoe it is also known as data selector.
ReplyDeletefor eg.
if there is 4:1 mux which has 4 inputs 'I0', 'I1','I2','I3' has select inputs 'S1' and 'S2' and ouput 'Y'.then the Truth table will be:
SELECTED INPUTS (OUTPUT)
S1 S2 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
online vlsi training
ReplyDeleteOnline training is benefited also in term of interaction with students from different region worldwide, which will make your communication skills better and also you can hear the doubt of different students from different region which might be not in your mind.